Tag Archives: Parser Design

Altera OPRA FAST Parser Design Example for FPGA and high frequency trading aka HFT use case

Altera OPRA FAST Parser Design Example for FPGA and high frequency trading aka HFT use case

This came in from an FPGA expert so thanks to him

This example demonstrates an Open Computing Language (OpenCLTM) implementation of a parser for the OPRA FAST standard. OPRA FAST is a standard developed for high-throughput and low-latency communication in financial markets; more information can be found at www.opradata.com.

The kernel parses incoming compressed OPRA Fast data from a UDP offload engine, and returns a subset of fields over Ethernet with the UDP offload engine. The UDP offload engines are represented as I/O channels to the kernel.

The kernel in this example is designed to process data at a line rate of 10G. More information is available in the OPRA FAST Overview and Implementation document available in the Downloads section below.

Features

  • Channels vendor extension
  • Low-latency for latency-sensitive application
  • Single work-item kernel

http://www.altera.com/support/examples/opencl/opra-fast.html

 

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