Tag Archives: MIC

Intel TBB C++ with MIC available for massive multicore HFT

Intel TBB C++ with MIC available for massive multicore HFT

C++  library built for massively-parallel multicore processors

 

https://en.wikipedia.org/wiki/Xeon_Phi

http://www.intel.com/content/www/us/en/architecture-and-technology/many-integrated-core/intel-many-integrated-core-architecture.html

https://www.threadingbuildingblocks.org

NOTE that most offloading libraries use OpenMP but it is commercial. I will stick with TBB for now.

http://stackoverflow.com/questions/615264/c-parallelization-libraries-openmp-vs-thread-building-blocks

http://www.drdobbs.com/parallel/cuda-vs-phi-phi-programming-for-cuda-dev/240144545

 

CUDA programmers need to remember that the Phi is designed as a coprocessor that runs Linux. Unlike GPUs that act only as accelerators, the Phi coprocessor has the ability to be used as a very capable support processor merely by compiling existing applications to run natively on it. Although this means that Phi coprocessors will probably not be a performance star for non-vector applications, they can still be used to speed applications via their many-core parallelism and high memory bandwidth.

http://arstechnica.com/gadgets/2016/08/nvidia-intel-xeon-phi-deep-learning-gpu/?comments=1

Xeon Phi might have the edge on Nvidia GPUs when it comes to double-precision FP. IIRC the performance of Pascal (and other GPUs) on DP is pretty awful, and that’s a big problem for many real-world HPC applications…

The poor double-precision performance is only an issue on consumer-grade Nvidia cards (e.g. anything that is not in their Tesla line of compute cards aimed toward HPC). In recent years, Nvidia has intentionally crippled DP performance on non-professional cards in order to ensure that those who need that aren’t tempted to purchase the much-cheaper Geforce devices instead…

Intel needs to stop playing this game of Xeon Phi vs GPGPUs like this. They are very different, and their strengths are different. After having benchmarked both of these many times, I realized that they should just be clear which problem domains are better on the Xeon Phi. GPGPU cores are “much dumber” and you get a lot more of them, which is perfectly fine for linear algebra. So any task which is asking the GPGPU to do straight repeated linear algebra (machine learning), obviously the GPGPU will be faster because that’s pretty much all it can do.

But the Xeon Phi has much faster data transfers, much faster memory allocation, can be used with standard MPI/OpenMP/OpenACC, and Knights Landing will be byte-compatible with x86. Do you have a code you already setup with MPI or OpenMP? As long as the memory requirements aren’t too high, you probably already set it up to minimize communications, and so you get a free 240 threads for every node you put a Xeon Phi in (without changing your program!). Does your program run for an indeterminate amount of time and have to allocate memory? Then the Xeon Phi will be faster. Do you have to use it simply as an accelerator, i.e. the problem size is too large for the memory of the card so you will have to keep pushing things back to the CPU? Then the Xeon Phi will be faster (and Knights Landing will have more memory, alleviating this problem even more).

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See 18;10 for vanilla pricing engine options example speed up

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How do you think Intel MIC architecture will be embraced by the HPC industry for high frequency trading?

How do you think Intel MIC architecture will be embraced by the HPC industry for high frequency trading? Which applications will be impacted the most? Do you think MIC will really offer an alternative to x86 for HPC?

TACC symposium and programming two SMP on a chip devices

software.intel.com

 

 

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I really think it all breaks down to MIC’s performance against the hardware that is currently being used in this application space. Any “processor” whether MIC or GPU that can be streamlined to run code compiled for it and not have to worry about handling any of the other systems functions is a great tool, … If it can be run parallel w/ Error correcting and out perform whats on the market now im sure that MIC will make a huge impact on the HPC market.

I’m quite excited to see it in action, Intel has made some extremely major changes to their products over the past few years and dramatically improved their performance and anything to make their products even faster is a better thing.

I don’t see it as an “alternative” for x86 HPC, but more of an additional tool for HPC.

 

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I guess in a real way you are correct that it may not necessarily need to be an alternative to x86 for HPC… especially because, in theory, x86 codes will recompile w/o changes and be able to run on MIC. I think this is key to adoption of MIC, whereas with FPGAs and GPUs (to some degree) you have to rewrite your code.

 

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Will HPC developers “just recompile and run” on Intel MIC to get useful application performance?

Will HPC developers “just recompile and run” on Intel MIC to get useful application performance? (read NVIDIA blog: http://blogs.nvidia.com/2012/04/no-free-lunch-for-intel-mic-or-gpus/)
==it’s not at all classy to post such a negative sounding poll about your competitor.
==You’re expecting too much from nvidia…
OTOH, Intel could argue that if you go for CUDA, you might find your development time increase much more than if you simply adapted your current and working code to MIC, while still using the same tools. So, you see, it cuts both ways …==From a HPC end-user’s point of view, it’s always great to see some new competitions coming out.
==yes it is good to have competitions In fact we have 2 very different propositions to do acceleration At the end we select on cost of computation A solution harder to program but delivering a better TCO will be selected by most customers requiring large scale A solution significantly easier to program will be selected by a wide range of new users in particular in the small and medium scale But tacking benefit of a GPU or MIC will stay a hard problem in most cases whatever the simplicit of programming in particular because the classical X86 will continue to be a strong solution and we see another option “low power” on our radar of solutions for large scale computations
==Interesting, though I’m inclined to say it skips one of the main points. Automony thats what intels mic offers, because you have branch instructions etc you can give it a complex task not just jobs. Truthfully haven’t seen any stats on how much beifit that will bring but it sounds interesting.
==Yes it seems clear MIC open acceleration to asignificantly wider range of problems; because MIC is simply an X86 with lot of cores If cheap and performant we can expect a large set of new opportunities

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GPU VS MIC which one do you want to try for quant development

GPU VS MIC which one do you want to try for quant development

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I already tried some stuff with GPU, so MIC seems like the next step

 

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No option for FPGA?

 

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what does FPGS mean?

 

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Field Programmable Gate Arrays.

They are extremely parallel but not as good for floating point as GPUs but in general better for other fixed data types.

Unfortunately the really fast high density ones tend to be really expensive, not to mention the programming model makes it less common…

http://lmgtfy.com/?q=fpga+hpc

 

 

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