For HFT: FPGA notes with potential capabilities thanks to Matlab’s Simulink and HDL Code Generation
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Current HFT operation are using FPGA so here is some proof with notes:

Some notes about FPGA with job options:
1. It is quite clear there are more jobs for FPGA vs CUDA/GPU. Some example job descriptions according to Dice in the world of finance:
http://seeker.dice.com/jobsearch/servlet/JobSearch?NUM_PER_PAGE=30&op=300&Ntk=JobSearchRanking&N=0&No=30&FRMT=0&FREE_TEXT=fpga&LOCATION_OPTION=2&Ntx=mode+matchall&QUICK=1&SORTSPEC=0&DAYSBACK=30&Hf=0&RADIUS=64.37376
http://seeker.dice.com/jobsearch/servlet/JobSearch?op=302&dockey=xml/a/0/a06f6051e2be624a1d4149bc69aa24d6@endecaindex&source=19&FREE_TEXT=fpga&rating=99
http://seeker.dice.com/jobsearch/servlet/JobSearch?op=302&dockey=xml/1/f/1f8d3b745731ce6bea1b9210b5cf0a99@endecaindex&source=19&FREE_TEXT=fpga&rating=99
There are no pay rates but believe me FPGA developers are top dogs in HFT shops!

2. Standard make Xilinx maker has some ‘affordable’ level boards for around $100-200.
http://www.xilinx.com/products/boards_kits/university/index.htm
A $1700 evaluation kit:
http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm
Ouch! FPGA is not cheap or easy to develop in. Nor is it easy or is it?

3. FPGA Software development with R and Matlab
Matlab appears to have a solution:
http://www.mathworks.com/fpga-design/
Nothing for R: http://www.r-bloggers.com/?s=fpga
I guess another reasons for Matlab. I have verified also there is something called Simulink HDL Code Generation. The help summarizes:
Simulink® HDL Coder™ software lets you generate hardware description language (HDL) code based on Simulink® models and Stateflow® finite-state machines. The coder brings the Model-Based Design approach into the domain of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) development. Using the coder, system architects and designers can spend more time on fine-tuning algorithms and models through rapid prototyping and experimentation and less time on HDL coding.

Typically, you use a Simulink model to simulate a design intended for realization as an ASIC or FPGA. Once satisfied that the model meets design requirements, you run the Simulink HDL Coder compatibility checker utility to examine model semantics and blocks for HDL code generation compatibility. You then invoke the coder, using either the command line or the graphical user interface. The coder generates VHDL or Verilog code that implements the design embodied in the model.

Usually, you also generate a corresponding test bench. You can use the test bench with HDL simulation tools to drive the generated HDL code and evaluate its behavior. The coder generates scripts that automate the process of compiling and simulating your code in these tools. You can also use EDA Simulator Link™, software from MathWorks® to cosimulate generated HDL entities within a Simulink model.

The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation. The design and test process is fully iterative. At any point, you can return to the original model, make modifications, and regenerate code.

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This $300 card was recommended

http://www.nallatech.com/PCI-Express-FPGA-Cards/pcie-287n-7-series-fpga-network-processing-card.html

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