Someone on my Youtube channel set the record straight about FPGA development generated by Matlab Simulink HDL Coder toolbox
This is imporant from a Youtube channel viewer:
It is truly awesome how Simulink generates C/C++ code for you. However, if you want to use HDL to “program” an FPGA (i.e. turn HDL code into a physical design), the code must be synthesizable. Only a subset of Verilog/VHDL is synthesizable.
If you try to generate either Verilog or VHDL code for your current design, I can guarantee it’ll generate a non-synthesizable code which means that even if you have an FPGA, you won’t be able to use it. I really wish it was that simple though 🙂
NOTE I now post my TRADING ALERTS into my personal FACEBOOK ACCOUNT and TWITTER. Don't worry as I don't post stupid cat videos or what I eat!