Someone on my Youtube channel set the record straight about FPGA development generated by Matlab Simulink HDL Coder toolbox

(Last Updated On: January 13, 2013)
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Someone on my Youtube channel set the record straight about FPGA development generated by  Matlab Simulink HDL Coder toolbox

This is imporant from a Youtube channel viewer:

It is truly awesome how Simulink generates C/C++ code for you. However, if you want to use HDL to “program” an FPGA (i.e. turn HDL code into a physical design), the code must be synthesizable. Only a subset of Verilog/VHDL is synthesizable.
If you try to generate either Verilog or VHDL code for your current design, I can guarantee it’ll generate a non-synthesizable code which means that even if you have an FPGA, you won’t be able to use it. I really wish it was that simple though 🙂

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Hi i there My name is Bryan Downing. I am part of a company called QuantLabs.Net This is specifically a company with a high profile blog about technology, trading, financial, investment, quant, etc. It posts things on how to do job interviews with large companies like Morgan Stanley, Bloomberg, Citibank, and IBM. It also posts different unique tips and tricks on Java, C++, or C programming. It posts about different techniques in learning about Matlab and building models or strategies. There is a lot here if you are into venturing into the financial world like quant or technical analysis. It also discusses the future generation of trading and programming Specialties: C++, Java, C#, Matlab, quant, models, strategies, technical analysis, linux, windows P.S. I have been known to be the worst typist. Do not be offended by it as I like to bang stuff out and put priorty of what I do over typing. Maybe one day I can get a full time copy editor to help out. Do note I prefer videos as they are much easier to produce so check out my many video at